Masterclock TCDS Series Spécifications télécharger pdf (Page 23)

Data Sheet AD1974

Rev. D | Page 23 of 24

APPLICATION CIRCUITS

Typical applications circuits are shown in Figure 17 and Figure 18. Figure 17 shows a typical ADC input filter circuit. Recommended loop

filters for LR clock and master clock as the PLL reference are shown in Figure 18.

OP275

–

OP275

–

5.76kΩ

5.76kΩ 237Ω

5.76kΩ

120p

600Z

UDIO

INPUT

100pF

5.76kΩ

120pF

4.7µF

237Ω

4.7µF

100pF

1nF

NP0

1nF

NP0

ADCxN

ADCxP

06614-023

Figure 17. Typical ADC Input Filter Circuit

39nF

2.2nF

LRCL

VDD2

3.32kΩ

5.6nF

390pF

MCLK

AVDD2

562Ω

06614-027

Figure 18. Recommended Loop Filters for LRCLK or MCLK PLL Reference

1 2 ... 18 19 20 21 22 23 24

4 ADC with PLL 1
192 kHz, 24-Bit ADC 1
TABLE OF CONTENTS 2
SPECIFICATIONS 3
ABSOLUTE MAXIMUM RATINGS 7
06614-020 8
AD1974 Data Sheet 10
Data Sheet AD1974 11
THEORY OF OPERATION 11
CONTROL REGISTERS 18
06614-059 21
6614-060 22
06614-027 23
OUTLINE DIMENSIONS 24

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Masterclock TCDS Series Spécifications Page 23

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