Masterclock TCDS Series Spécifications télécharger pdf (Page 20)

AD1974 Data Sheet

Rev. D | Page 20 of 24

Table 20. AUXPORT Control 2

Bit Value Function Description

0

0

Reserved

1 Reserved

2:1 00 Reserved

01 Reserved

10 Reserved

11 Reserved

4:3 00 24 Word width

01 20

10 Reserved

11 16

5 0 Reserved

1 Reserved

7:6 00 Reserved

ADC CONTROL REGISTERS

Table 21. ADC Control 0

Bit Value Function Description

0 0 Normal Power-down

1 Power down

1 0 Off High-pass filter

1 On

2 0 Unmute ADC1L mute

1 Mute

3 0 Unmute ADC1R mute

1 Mute

4 0 Unmute ADC2L mute

1 Mute

5 0 Unmute ADC2R mute

1 Mute

7:6 00 32 kHz/44.1 kHz/48 kHz Output sample rate

01

64 kHz/88.2 kHz/96 kHz

10 128 kHz/176.4 kHz/192 kHz

11 Reserved

Table 22. ADC Control 1

Bit Value Function Description

1:0 00 24 Word width

01 20

10 Reserved

11 16

4:2 000 1 SDATA delay (BCLK periods)

001 0

010 8

011 12

100 16

101 Reserved

110 Reserved

111 Reserved

1 2 ... 15 16 17 18 19 20 21 22 23 24

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