Masterclock TCDS Series Spécifications télécharger pdf (Page 17)

Data Sheet AD1974

Rev. D | Page 17 of 24

AUX

ADC 1

LRCLK

BCLK

DATA

MCLK

AUX

ADC 2

LRCLK

BCLK

DATA

MCLK

30MHz

12.288MHz

SHARC IS RUNNING

IN SLAVE MODE

(INTERRUPT-DRIVEN)

SHARC

AD1974

TDM MASTER

AUX MASTER

FSYNC-TDM (RFS)

RxCLK

RxDATA

TxCLK

TFS (NC)

AUXBCLK

AUXLRCLK

AUXDATA1

AUXDATA2

MCLK

ASDATA1

ALRCLK ABCLK

06614-019

Figure 14. Example of AUX Mode Connection to SHARC® (AD1974 as TDM Master/AUX Master Shown)

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