Masterclock TCDS Series Fiche technique

[AK4646] MS0557-E-06 2011/06 - 1 - GENERAL DESCRIPTION The AK4646 features a stereo CODEC with a built-in Microphone-Amplifier and Spea

[AK4646] MS0557-E-06 2011/06 - 10 - Parameter min typ max UnitsSpeaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF,OVOL=0dB, CL=3μF, Rser

[AK4646] MS0557-E-06 2011/06 - 11 - FILTER CHARACTERISTICS (Ta = 25°C; AVDD =2.2 ∼ 3.6V, DVDD =1.6 ∼ 3.6V, SVDD =2.2 ∼ 4.0V; fs=44.1kHz; DEM=

[AK4646] MS0557-E-06 2011/06 - 12 - SWITCHING CHARACTERISTICS (Ta = 25°C; AVDD =2.2 ∼ 3.6V, DVDD =1.6 ∼ 3.6V, SVDD =2.2 ∼ 4.0V; CL=20pF) Param

[AK4646] MS0557-E-06 2011/06 - 13 - Parameter Symbol min typ max UnitsPLL Slave Mode (PLL Reference Clock = LRCK pin) LRCK Input Timing Fr

[AK4646] MS0557-E-06 2011/06 - 14 - Parameter Symbol min typ max UnitsAudio Interface Timing Master Mode BICK “↓” to LRCK Edge (Note 27) tM

[AK4646] MS0557-E-06 2011/06 - 15 - Timing Diagram LRCK1/fCLKMCKItCLKH tCLKLVIHVIL1/fMCKMCKOtMCKL50%DVDD1/fstLRCKH tLRCKL50%DVDDDuty = tLRC

[AK4646] MS0557-E-06 2011/06 - 16 - 1/fCLKMCKItCLKH tCLKLVIHVIL1/fsLRCKVIHVILtBCKBICKtBCKH tBCKLVIHVILtLRCKH tLRCKLfMCKMCKOtMCKL50%DVDDdMCK =

[AK4646] MS0557-E-06 2011/06 - 17 - LRCKVIHVILtBLRBICKVIHVILtLRDSDTO 50%DVDDtLRBtBSDtSDSSDTIVILtSDHVIHMSB Figure 6. Audio Interface Timing (P

[AK4646] MS0557-E-06 2011/06 - 18 - CSN CCLK 50% DVDDCDTIO VIH D3 D2 D1 D0 tCCZ tDCDVIL VIH VIL Hi-Z Clock, H or L Figure 9. Read Data Out

[AK4646] MS0557-E-06 2011/06 - 19 - OPERATION OVERVIEW System Clock There are the following five clock modes to interface with external de

[AK4646] MS0557-E-06 2011/06 - 2 - 6. Sampling Rate: • PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz • PLL Slave Mode (BICK pin): 7.35kHz ∼ 48kHz

[AK4646] MS0557-E-06 2011/06 - 20 - PLL Mode When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock tha

[AK4646] MS0557-E-06 2011/06 - 21 - PLL Unlock State 1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) In this mode, LRCK and BICK pins

[AK4646] MS0557-E-06 2011/06 - 22 - PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) When an external clock (12MHz, 13.5MHz, 24MHz or 27MHz

[AK4646] MS0557-E-06 2011/06 - 23 - PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input cl

[AK4646] MS0557-E-06 2011/06 - 24 - b) PLL reference clock: BICK or LRCK pin Sampling frequency corresponds to 7.35kHz to 48kHz by changing F

[AK4646] MS0557-E-06 2011/06 - 25 - EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) When PMPLL bit is “0”, the AK4646 becomes EXT mode. Mas

[AK4646] MS0557-E-06 2011/06 - 26 - EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) The AK4646 becomes EXT Master Mode by setting PMPLL bi

[AK4646] MS0557-E-06 2011/06 - 27 - System Reset Upon power-up, the PDN pin should be “L” and be changed from “L” to “H” after all power su

[AK4646] MS0557-E-06 2011/06 - 28 - LRCKBICK(32fs)SDTO(o)SDTI(i)015 1415 1411013132377654321065431029 1112131415 012315 14 1310151576543210109

[AK4646] MS0557-E-06 2011/06 - 29 - LRCKBICK(32fs)SDTO(o)SDTI(i)015 1415 141102377654321065431029 1112131415 012315 141076543210109 1112131415

[AK4646] MS0557-E-06 2011/06 - 3 - Ordering Guide AK4646EN −30 ∼ +85°C 32pin QFN (0.5mm pitch) AK4646EZ −30 ∼ +85°C

[AK4646] MS0557-E-06 2011/06 - 30 - MIC/LINE Input Selector The AK4646 has an input selector. When MDIF1 and MDIF2 bits are “0”, INL and IN

[AK4646] MS0557-E-06 2011/06 - 31 - MIC Gain Amplifier The AK4646 has a gain amplifier for microphone input. The gain of MIC-Amp is selecte

[AK4646] MS0557-E-06 2011/06 - 32 - Digital Block The digital block consists of block diagram as shown in Figure 24. HPF ~ ALC blocks are u

[AK4646] MS0557-E-06 2011/06 - 33 - PMADL PMADR PMDACDAFILLOOP Figure 24 SW Mode bit bit bit bit bit SW1 SW2 Figure Recording Mode 1 1 x

[AK4646] MS0557-E-06 2011/06 - 34 - Digital Programmable Filter Circuit (1) High Pass Filter (HPF) Normally, this HPF is used for a Wind-

[AK4646] MS0557-E-06 2011/06 - 35 - (3) Stereo Separation Emphasis Filter (FIL3) FIL3 is used to emphasize the stereo separation of stereo m

[AK4646] MS0557-E-06 2011/06 - 36 - (4) Gain Compensation (EQ0) Gain Compensation is used to compensate the frequency response and the gain

[AK4646] MS0557-E-06 2011/06 - 37 - (5) 5-band Notch This block can be used as Equalizer or Notch Filter. 5-band Equalizer (EQ1, EQ2, EQ3, E

[AK4646] MS0557-E-06 2011/06 - 38 - ALC Operation The ALC (Automatic Level Control) is operated by ALC block when ALC bit is “1”. When both

[AK4646] MS0557-E-06 2011/06 - 39 - 2. ALC Recovery Operation The ALC recovery operation waits for the WTM2-0 bits (Table 26) to be set afte

[AK4646] MS0557-E-06 2011/06 - 4 - Comparison with AK4642/AK4643 1. Function Function AK4642 AK4643 AK4646 AVDD 2.6V ∼ 3.6V 2.2V ∼ 3.6V DV

[AK4646] MS0557-E-06 2011/06 - 40 - IREF7-0bits GAIN(0dB) Step F1H +36.0 F0H +35.625 EFH +35.25 : : E1H +30.0 (default) : : 92H

[AK4646] MS0557-E-06 2011/06 - 41 - 3. The Volume at the ALC Operation The current volume value at the ALC operation is reflected by VOL7-0

[AK4646] MS0557-E-06 2011/06 - 42 - fs=8kHz fs=44.1kHz Register Name Comment Data Operation Data Operation LMTH1-0 Limiter detection Level

[AK4646] MS0557-E-06 2011/06 - 43 - Input Digital Volume (Manual Mode) The input digital volume becomes a manual mode at ALC1 bit = “0” whe

[AK4646] MS0557-E-06 2011/06 - 44 - Output Digital Volume (Manual Mode) The ALC block becomes output digital volume (manual mode) by settin

[AK4646] MS0557-E-06 2011/06 - 45 - De-emphasis Filter The AK4646 includes the digital de-emphasis filter (tc = 50/15μs) which corresponds

[AK4646] MS0557-E-06 2011/06 - 46 - Analog Mixing: Mono Input When the PMBP bit is set to “1”, the mono input is powered-up. When the BEEPS

[AK4646] MS0557-E-06 2011/06 - 47 - Stereo Line Output (LOUT/ROUT pins) When DACL bit is “1”, Lch/Rch signal of DAC is output from the LOUT

[AK4646] MS0557-E-06 2011/06 - 48 - [Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)] PMLO bit LO PS bit LOUT,

[AK4646] MS0557-E-06 2011/06 - 49 - Speaker Output Power supply for Speaker-Amp (SVDD) is 2.2V to 4.0V. In case of dynamic (electromagnetic

[AK4646] MS0557-E-06 2011/06 - 5 - PIN/FUNCTION No. Pin Name I/O Function 1 MPWR O MIC Power Supply Pin 2 VCOM O Common Voltage Output

[AK4646] MS0557-E-06 2011/06 - 50 - <Caution for using Piezo Speaker> When a piezo speaker is used, resistances more than 10Ω should be

[AK4646] MS0557-E-06 2011/06 - 51 - <Speaker-Amp Control Sequence> Speaker-Amp is powered-up/down by PMSPK bit. When PMSPK bit is “0”,

[AK4646] MS0557-E-06 2011/06 - 52 - Serial Control Interface Internal registers may be written by using the 3-wire µP interface pins (CSN,

[AK4646] MS0557-E-06 2011/06 - 53 - Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 1 0 PMVCMPMBP PMSPK PML

[AK4646] MS0557-E-06 2011/06 - 54 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 30H Digital Filter Select 2 0 0 0 EQ5 EQ4 EQ3 EQ2 EQ1 31

[AK4646] MS0557-E-06 2011/06 - 55 - Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 1 0 PMVCM PMBP

[AK4646] MS0557-E-06 2011/06 - 56 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Power Management 2 0 0 0 0 M/S 0 MCKO PMPLLR/W R R

[AK4646] MS0557-E-06 2011/06 - 57 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H Signal Select 2 DAFIL LOPSMGAIN1SPKG1 SPKG0 BEEP

[AK4646] MS0557-E-06 2011/06 - 58 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 06H Timer Select 0 WTM2 ZTM1 ZTM0 WTM1 WTM0 RFST1 RFST0R/

[AK4646] MS0557-E-06 2011/06 - 59 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H ALC Mode Control 2 IREF7 IREF6 IREF5 IREF4 IREF3 IRE

[AK4646] MS0557-E-06 2011/06 - 6 - Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification P

[AK4646] MS0557-E-06 2011/06 - 60 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0EH Mode Control 3 READ LOOP SMUTE OVOLC DATT1 DATT0 DEM

[AK4646] MS0557-E-06 2011/06 - 61 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 10H Power Management 3 0 0 0 MDIF2 MDIF1 INR INL

[AK4646] MS0557-E-06 2011/06 - 62 - LPF: LPF Coefficient Setting Enable 0: Disable (default) 1: Enable When LPF bit is “1”, the settings of F2

[AK4646] MS0557-E-06 2011/06 - 63 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 30H Digital Filter Select 2 0 0 0 EQ5 EQ4 EQ3 EQ2 EQ1

[AK4646] MS0557-E-06 2011/06 - 64 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 32H E1 Co-efficient 0 E1A7 E1A6 E1A5 E1A4 E1A3 E1A2 E1A1

[AK4646] MS0557-E-06 2011/06 - 65 - SYSTEM DESIGN Figure 37 shows the system connection diagram for the AK4646. An evaluation board [AKD4646]

[AK4646] MS0557-E-06 2011/06 - 66 - 1. Grounding and Power Supply Decoupling The AK4646 requires careful attention to power supply and grou

[AK4646] MS0557-E-06 2011/06 - 67 - CONTROL SEQUENCE Clock Set up When ADC or DAC is powered-up, the clocks must be supplied. 1. PLL Mast

[AK4646] MS0557-E-06 2011/06 - 68 - 2. PLL Slave Mode (LRCK or BICK pin) PMPLL bit(Addr:01H, D0)Internal Clock(1)Power SupplyPDN pinPMVCM bit

[AK4646] MS0557-E-06 2011/06 - 69 - 3. PLL Slave Mode (MCKI pin) BICK pinLRCK pinMCKO bit(Addr:01H, D1)PMPLL bit(Addr:01H, D0)(1)Power Supply

[AK4646] MS0557-E-06 2011/06 - 7 - ABSOLUTE MAXIMUM RATINGS (AVSS=DVSS=SVSS=0V; Note 3) Parameter Symbol min max Units Power Supplies: Analog

[AK4646] MS0557-E-06 2011/06 - 70 - 4. EXT Slave Mode (1)Power SupplyPDN pinPMVCM bit(Addr:00H, D6)(2) (3)LRCK pinBICK pin(4)Input(4)MCKI pin

[AK4646] MS0557-E-06 2011/06 - 71 - MIC Input Recording (Stereo) FS3-0 bits(Addr:05H, D5&D2-0)MIC Control(Addr:02H, D2-0)PMADL/R bit(Add

[AK4646] MS0557-E-06 2011/06 - 72 - Speaker-amp Output FS3-0 bits(Addr:05H, D5&D2-0)OVL/R7-0 bits(Addr:0AH&0DH, D7-0)PMDAC bit(Addr

[AK4646] MS0557-E-06 2011/06 - 73 - Mono signal output from Speaker-Amp DACS bit(Addr:02H, D5)PMSPK bit(Addr:00H, D4)BEEPS bit(Addr:02H, D6

[AK4646] MS0557-E-06 2011/06 - 74 - Stereo Line Output FS3-0 bits(Addr:05H, D5&D2-0)OVL/R7-0 bits(Addr:0AH&0DH, D7-0)PMDAC bit(Addr

[AK4646] MS0557-E-06 2011/06 - 75 - Stop of Clock Master clock can be stopped when ADC and DAC are not used. 1. PLL Master Mode External

[AK4646] MS0557-E-06 2011/06 - 76 - 3. PLL Slave (MCKI pin) External MCKIPMPLL bit(Addr:01H, D0)Input(1)(2)MCKO bit(Addr:01H, D1)(1) ExampleA

[AK4646] MS0557-E-06 2011/06 - 77 - PACKAGE (AK4646EN) 32pin QFN (Unit: mm)4.75 ± 0.105.00 ± 0.104.75 ± 0.100.500.2324 172511610.010.083289C0

[AK4646] MS0557-E-06 2011/06 - 78 - PACKAGE (AK4646EZ) 32pin QFN (Unit: mm)2.4 ± 0.10.40.18 ± 0.050.00 MIN0.05 MAX0.65 MAX2.4 ± 0.11916254.

[AK4646] MS0557-E-06 2011/06 - 79 - MARKING (AK4646EN) AK4646XXXXX1AKM XXXXX: Date code identifier (5 digits) MARKING (AK4646EZ) 46

[AK4646] MS0557-E-06 2011/06 - 8 - ANALOG CHARACTERISTICS (Ta=25°C; AVDD=DVDD=SVDD=3.3V; AVSS=DVSS=SVSS=0V; fs=44.1kHz, BICK=64fs; Signal Fre

[AK4646] MS0557-E-06 2011/06 - 80 - REVISION HISTORY Date (YY/MM/DD) Revision Reason Page Contents 07/05/14 02 First Edition 10/01/07

[AK4646] MS0557-E-06 2011/06 - 81 - IMPORTANT NOTICE z These products and their specifications are subject to cha

[AK4646] MS0557-E-06 2011/06 - 9 - Parameter min typ max UnitsDAC Characteristics: Resolution - - 16 Bits Stereo Line Output Characteristics: